A 2
نویسندگان
چکیده
A Phase Locked Loop (PLL) design based on a new phase detector (PD) is presented. It can be used as a part of data/clock recovery (DCR) systems targeting the applications of 2Gbit/s-3Gbit/s range ethernet and optic fiber transceivers in current semiconductor processes. A key component in the circuit is a new non-sequential PD that provides for very high speed operation. Using TSMC 0.25u CMOS process device models and the HSPICE simulator, results show that the PLL can operate at 2.5GHz over process corners and a 0°C to 100°C temperature range. Total power dissipation is 40mW with a single 2.5V power supply.
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